1. Field of the Invention
The present invention relates generally to alignment systems and more particularly their uses in lithographic apparatus or overlay measurement apparatus.
2. Description of the Related Art
A lithographic apparatus is a machine that applies a desired pattern onto a target portion of a substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that circumstance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising part of, one or several dies) on a substrate (e.g., a silicon wafer) that has a layer of radiation-sensitive material (resist). In general, a single substrate will contain a network of adjacent target portions that are successively exposed. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion in one go, and so-called scanners, in which each target portion is irradiated by scanning the pattern through the projection beam in a given direction (the “scanning”-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction.
In a manufacturing process using such a lithographic projection apparatus, in an imaging step, the pattern is imaged onto the substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing,” Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
For the above mentioned manufacturing process and especially during the imaging step it is necessary to position the substrate and the mask on respective object tables with a high accuracy with regard to each other. For this purpose alignment marks are provided on the substrate and in the mask. An alignment system such as described for example in WO 98/39689 or U.S. Pat. No. 4,778,275 incorporated herein by reference, can be used to align a mark in the mask with respect to a corresponding mark on the substrate. If a mark on a substrate is not correctly aligned to the corresponding reference point in the mask this alignment error will cause an error in the super-positioning of two images exposed on successive layers on the substrate. This error in the super-positioning of two images is generally called an overlay error. If a large overlay error occurs, the substrate or a device finally cut out of the substrate may be rejected during a quality inspection. The overlay error is determined in an overlay measurement apparatus by measuring the shift of overlay metrology targets. One part of each target is printed in a first layer. Another part of each target is printed in a second layer or in an adjacent image in the first layer. The overlay error at a specific location of the substrate is equal to the shift between the two printed parts of the target.
One of the first steps that is accomplished when a new substrate is to be manufactured in a lithographic projection apparatus is that alignment marks are exposed on the first layer of resist on the substrate. These marks will be used for aligning the subsequent images to be exposed in subsequent layers of resist on the substrate. The deposition of additional layers and the processing necessary to finish off these subsequent layers may affect the alignment mark such that the alignment mark appears to be shifted in the plane of the substrate. This may cause overlay errors between layers on the substrate. One trend in the industry to reduce such overlay errors is to expose more alignment marks in higher resist layers on the substrate, that are aligned themselves with the alignment marks in the first resist layer. These alignment marks in higher resist layers are, then, used for alignment purposes in these higher resist layers and above.
In each resist layer there may be many such alignment marks, e.g., 100 or even more. Not all these alignment marks will be used since not all of them are, e.g., suitable to be used or using them all will take too much time without improving the accuracy of the measurement significantly. Therefore, two or more suitable alignment marks have to be selected from the set of marks in each resist layer. In the past, e.g., 2 mark pairs (a mark pair is a combination of an X mark and a Y mark located substantially close together, that can be used to determine both X and Y position) per resist layer were used for alignment purposes. Nowadays, the industry is moving to measuring more alignment marks on the substrate to get more accurate information about the actual position of the substrate on the wafer stage and about it's actual shape. In a dual stage machine, e.g., 16 mark pairs may be used without overall throughput impact. This information will be used during exposure to achieve best overlay to the layer in which the marks are exposed.
A still further trend in the industry is that alignment marks are used which are exposed in scribelines between product dies. These alignment marks are exposed with the product and the overlay metrology targets in one lithography step.
Consequence of these two trends is that alignment marks are present in a periodic X,Y pattern on the substrate at fixed positions with respect to a centre of all images. Operators or process engineers of the lithographic apparatus have the task to select a sub-set out off all these alignment marks present on the substrate, which sub-set meets certain predetermined criteria. However, these operators are confronted with several problems:
They need to have a method to select alignment marks exposed at the same location of a physical image on the substrate over multiple layers. This does not mean that they want to align on the same mark over these multiple layers. As explained above, nowadays, most operators expose a new mark after some process steps with a small offset in the scribeline close to a previous mark in a lower resist layer on which they have aligned.
They need to select a set of mark pairs (X-mark and Y-mark=1 pair) which will give them the best overlay out of all marks available on the substrate. Depending on an underlying wafer deformation model some mark distribution models are possible.
A special problem is Wafer Capture. In the phase of Wafer Capture, the rotation of the substrate is not well known and the X and Y mark (which are in different scribelines) which form a X-Y mark pair need to be as close as possible, while the mark pairs themselves should be apart as far as possible.
Moreover, a generic problem for operators is that they need to optimize a selected mark-layout for best overlay and also for maximum productivity. This means that the time needed to measure all marks need to be as short as possible in order to reduce loss of throughput. Thus, operators should optimize a selected alignment mark layout on the substrate and have to have all the knowledge to find the optimum set for 1) overlay, 2) productivity and 3) robustness (i.e., reliability).